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| ? 2009 microchip technology inc. ds22039d-page 1 mcp4725 features ? 12-bit resolution ? on-board non-volatile memory (eeprom) ? 0.2 lsb dnl (typical) ? external a0 address pin ? normal or power-down mode ? fast settling time: 6 s (typical) ? external voltage reference (v dd ) ? rail-to-rail output ? low power consumption ? single-supply operation: 2.7v to 5.5v ?i 2 c tm interface: - eight available addresses - standard (100 kbps), fast (400 kbps), and high-speed (3.4 mbps) modes ? small 6-lead sot-23 package ? extended temperature range: -40c to +125c applications ? set point or offset trimming ? sensor calibration ? closed-loop servo control ? low power portable instrumentation ? pc peripherals ? data acquisition systems block diagram description the mcp4725 is a low-power, high accuracy, single channel, 12-bit buffered voltage output digital-to- analog convertor (dac) with non-volatile memory (eeprom). its on-board prec ision output amplifier allows it to achieve rail-to-rail analog output swing. the dac input and configuration data can be programmed to the non-vo latile memory (eeprom) by the user using i 2 c interface command. the non-volatile memory feature enables the dac device to hold the dac input code during power-off time, and the dac output is available immediately after power-up. this feature is very useful when the dac device is used as a supporting device for other devices in the network. the device includes a power-on-reset (por) circuit to ensure reliable power-up and an on-board charge pump for the eeprom programming voltage. the dac reference is driven from v dd directly. in power- down mode, the output amplifier can be configured to present a known low, medium, or high resistance output load. the mcp4725 has an external a0 address bit selection pin. this a0 pin can be tied to v dd or v ss of the user?s application board. the mcp4725 has a two-wire i 2 c? compatible serial interface for standard (100 khz), fast (400 khz), or high speed (3.4 mhz) mode. the mcp4725 is an ideal dac device where design simplicity and small footprint is desired, and for applications requiring the dac device settings to be saved during power-off time. the device is available in a small 6-pin sot-23 package. package type resistive power-on reset charge pump eeprom i 2 c interface logic input register dac register op amp power-down control v dd v ss scl sda v out a0 string dac 3 v dd scl sda v ss a0 sot-23-6 v out 2 1 4 5 6 mcp4725 12-bit digital-to-analog co nverter with eeprom memory in sot-23-6
mcp4725 ds22039d-page 2 ? 2009 microchip technology inc. notes: ? 2009 microchip technology inc. ds22039d-page 3 mcp4725 1.0 electrical characteristics absolute maximum ratings? v dd ...................................................................................6.5v all inputs and outputs w.r.t v ss .................?0.3v to v dd +0.3v current at input pins ....................................................2 ma current at supply pins ...............................................50 ma current at output pins ...............................................25 ma storage temperature ...................................-65c to +150c ambient temp. with power applied .............-55c to +125c esd protection on all pins ................ 6kv hbm, 400v mm maximum junction temperature (t j ) ......................... +150c ? notice: stresses above those listed under ?maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation listings of this specif ication is not implied. exposure to maximum rating conditions for extended periods may affect device reliability electrical characteristics electrical specifications: unless otherwise indicated, all parameters apply at v dd = + 2.7v to 5.5v, v ss = 0v, r l = 5 k ? from v out to v ss , c l = 100 pf, t a = -40c to +125c. typical values are at +25c. parameter sym min typ max units conditions power requirements operating voltage v dd 2.7 5.5 v supply current i dd ? 210 400 a digital input pins are grounded, output pin (v out ) is not connected (unloaded), code = 000h power-down current i ddp ?0.06 2.0 a v dd = 5.5v power-on-reset threshold voltage v por ?2 ? v dc accuracy resolution n 12 ? ? bits code range = 000h to fffh inl error inl ? 2 14.5 lsb note 1 dnl dnl -0.75 0.2 0.75 lsb note 1 offset error v os 0.02 0.75 % of fsr code = 000h offset error drift v os /c ? 1 ? ppm/c -45c to +25c ? 2 ? ppm/c +25c to +85c gain error g e -2 -0.1 2 % of fsr code = fffh, offset error is not included. gain error drift g e /c ? -3 ? ppm/c output amplifier phase margin p m ? 66 ? degree() c l = 400 pf, r l = capacitive load stability c l ? ? 1000 pf r l = 5 k ? , note 2 slew rate sr ? 0.55 ? v/s short circuit current i sc ?15 24 ma v dd = 5v, v out = grounded output voltage settling time t s ?6 ? s note 3 note 1: test code range: 100 to 4000. 2: this parameter is ensure by design and not 100% tested. 3: within 1/2 lsb of the final value when code changes fr om 1/4 to 3/4 (400h to c00h) of full scale range. 4: logic state of external address selection pin (a0 pin). mcp4725 ds22039d-page 4 ? 2009 microchip technology inc. power up time t pu ?2.5 ? sv dd = 5v ?5 ? sv dd = 3v exit power-down mode, (started from falling edge of ack pulse) dc output impedance r out ?1 ? normal mode (v out to v ss ) ?1 ? k power-down mode 1 (v out to v ss ) ?100 ? k power-down mode 2 (v out to v ss ) ?500 ? k power-down mode 3 (v out to v ss ) supply voltage power-up ramp rate for eeprom loading v dd_ramp 1 ? ? v/ms validation only. dynamic performance major code transition glitch ? 45 ? nv-s 1 lsb change around major carry (from 800h to 7ffh) ( note 2) digital feedthrough ? <10 ? nv-s note 2 digital interface output low voltage v ol ? ? 0.4 v i ol = 3 ma input high voltage (sda and scl pins) v ih 0.7v dd ?? v input low voltage (sda and scl pins) v il ? ?0.3v dd v input high voltage (a0 pin) v a0-hi 0.8v dd ?? note 4 input low voltage (a0 pin) v a0-il ? ? 0.2v dd note 4 input leakage i li ? ? 1 a scl = sda = a0 = v ss or scl = sda = a0 = v dd pin capacitance c pin ?? 3 pf note 2 eeprom eeprom write time t write ?25 50 ms data retention ? 200 ? years at +25c, (note 2) endurance 1 ? ? million cycles at +25c, (note 2) electrical character istics (continued) electrical specifications: unless otherwise indicated, all parameters apply at v dd = + 2.7v to 5.5v, v ss = 0v, r l = 5 k ? from v out to v ss , c l = 100 pf, t a = -40c to +125c. typical values are at +25c. parameter sym min typ max units conditions note 1: test code range: 100 to 4000. 2: this parameter is ensure by design and not 100% tested. 3: within 1/2 lsb of the final value when code changes fr om 1/4 to 3/4 (400h to c00h) of full scale range. 4: logic state of external address selection pin (a0 pin). ? 2009 microchip technology inc. ds22039d-page 5 mcp4725 temperature characteristics electrical specifications: unless otherwise indicated, v dd = +2.7v to +5.5v, v ss =gnd. parameters sym min typ max units conditions temperature ranges specified temperature range t a -40 ? +125 c operating temperature range t a -40 ? +125 c storage temperature range t a -65 ? +150 c thermal package resistances thermal resistance, 6l-sot-23 ja ? 190.5 ? c/w mcp4725 ds22039d-page 6 ? 2009 microchip technology inc. notes: ? 2009 microchip technology inc. ds22039d-page 7 mcp4725 2.0 typical performance curves note: unless otherwise indicated, t a = +25c, v dd = +5.0v, v ss = 0v, r l = 5 k ? to v ss , c l = 100 pf. figure 2-1: dnl vs. code (v dd = 5.5v). figure 2-2: dnl vs. code and temperature (t a =-40cto+125c). figure 2-3: dnl vs. code (v dd =2.7v). figure 2-4: dnl vs. code and temperature (t a = -40c to +125c). figure 2-5: inl vs. code. figure 2-6: inl vs. code and temperature (v dd =5.5v). note: the graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes on ly. the performance characteristics listed herein are not tested or guaranteed. in some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore, outsi de the warranted range. -0.04 0 0.04 0.08 0.12 0.16 0 1024 2048 3072 4096 code dnl (lsb) -0.1 0 0.1 0.2 0.3 0 1024 2048 3072 4096 code dnl (lsb) v dd = 5.5v -0.1 0.0 0.1 0.2 0.3 0 1024 2048 3072 4096 code dnl (lsb) -0.1 0.0 0.1 0.2 0.3 0.4 0 1024 2048 3072 4096 code dnl (lsb) v dd = 2.7v -4 -3 -2 -1 0 1 2 0 1024 2048 3072 4096 code inl(lsb) 2.7v 5.5v -4 -3 -2 -1 0 1 2 0 1024 2048 3072 4096 code inl(lsb) +25c +125c - 40c +85c mcp4725 ds22039d-page 8 ? 2009 microchip technology inc. note: unless otherwise indicated, t a = +25c, v dd = +5.0v, v ss = 0v, r l = 5 k ? to v ss , c l = 100 pf. figure 2-7: inl vs. code and temperature (v dd =2.7v). figure 2-8: zero scale error vs. temperature (code = 000d). figure 2-9: full scale error vs. temperature (code = 4095d). figure 2-10: output error vs. temperature (code = 4000d). figure 2-11: i dd vs. temperature. -5 -4 -3 -2 -1 0 1 2 0 1024 2048 3072 4096 code inl(lsb) ta = -40 c ta = 25 c ta = 85 c ta = 125 c +125c - 40c +85c +25c -1 0 1 2 3 -40 -25 -10 5 20 35 50 65 80 95 110 125 temperature (c) zero scale error (mv) v dd = 5.5v v dd = 2.7v -60 -50 -40 -30 -20 -10 0 -40 -25 -10 5 20 35 50 65 80 95 110 125 temperature (c) full-scale error (mv) v dd = 2.7v v dd = 5.5v -5 -4 -3 -2 -1 0 1 2 3 -40 -25 -10 5 20 35 50 65 80 95 110 125 temperature (c) output error (mv) v dd = 2.7v v dd = 5.5v 0 50 100 150 200 250 300 350 400 450 -40 -25 -10 5 20 35 50 65 80 95 110 125 temperature(c) i dd (a) v dd = 2.7v v dd = 5v ? 2009 microchip technology inc. ds22039d-page 9 mcp4725 note: unless otherwise indicated, t a = +25c, v dd = +5.0v, v ss = 0v, r l = 5 k ? to v ss , c l = 100 pf. figure 2-12: i dd histogram . figure 2-13: i dd histogram. figure 2-14: offset error vs. temperature and v dd . figure 2-15: v out vs. resistive load. figure 2-16: source and sink current capability. figure 2-17: v in high threshold vs. temperature and v dd . 0 10 20 30 40 50 60 70 80 90 100 180 184 188 192 196 200 204 208 212 216 220 224 228 232 236 current (a) occurance v dd = 5v v dd = 2.7v 0 10 20 30 40 50 60 70 80 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 current (a) occurance 0.00 0.50 1.00 1.50 2.00 2.50 -40 -25 -10 5 20 35 50 65 80 95 110 125 temperature (c) offset error (mv) 2.7v 5.5v 0 1 2 3 4 5 6 012345 load resistance (k ? ) v out (v) v dd = 5v code = fffh 0 1 2 3 4 5 6 0481216 i source/sink (ma) v out (v) code = fffh code = 000h v dd = 5v 1.00 1.50 2.00 2.50 3.00 3.50 -40 -25 -10 5 20 35 50 65 80 95 110 125 temperature (c) v ih threshold (v) v dd = 5.5v v dd = 5.0v v dd = 2.7v mcp4725 ds22039d-page 10 ? 2009 microchip technology inc. note: unless otherwise indicated, t a = +25c, v dd = +5.0v, v ss = 0v, r l = 5 k ? to v ss , c l = 100 pf. figure 2-18: v in low threshold vs. temperature and v dd . figure 2-19: full scale settling time. figure 2-20: full scale settling time. figure 2-21: half scale settling time. figure 2-22: half scale settling time. figure 2-23: code change glitch. 0.50 0.70 0.90 1.10 1.30 1.50 1.70 1.90 2.10 2.30 2.50 -40 -25 -10 5 20 35 50 65 80 95 110 125 temperature (c) v il threshold (v) v dd = 5.5v v dd = 5.0v v dd = 2.7v full scale code change : 000h to fffh v out (2v/div) clk time (2 s/div) full scale code change : fffh to 000h v out (2v/div) clk time (2 s/div) half scale code change : 000h to 7ffh v out (2v/div) clk time (2 s/div) v out (2v/div) clk time (2 s/div) half scale code change : 7ffh to 000h code change : 800h to 7ffh v out (20 mv/div) time (1 s/div) ? 2009 microchip technology inc. ds22039d-page 11 mcp4725 note: unless otherwise indicated, t a = +25c, v dd = +5.0v, v ss = 0v, r l = 5 k ? to v ss , c l = 100 pf. figure 2-24: exiting power down mode. v out (2v/div) clk time (2 s/div) mcp4725 ds22039d-page 12 ? 2009 microchip technology inc. notes:. ? 2009 microchip technology inc. ds22039d-page 13 mcp4725 3.0 pin descriptions the descriptions of the pins are listed in table 3-1 . 3.1 analog output voltage (v out ) v out is an analog output voltage from the dac device. dac output amplifier drives this pin with a range of v ss to v dd . 3.2 supply voltage (v dd or v ss ) v dd is the power supply pin for the device. the voltage at the v dd pin is used as the supply input as well as the dac reference input. the power supply at the v dd pin should be clean as possible for a good dac performance. this pin requires an appropriate bypass capacitor of about 0.1 f (ceramic) to ground. an additional 10 f capacitor (tantalum) in para llel is also recommended to further attenuate high frequency noise present in application boards. the supply voltage (v dd ) must be maintained in the 2.7v to 5.5v range for specified operation. v ss is the ground pin and the current return path of the device. the user must connect the v ss pin to a ground plane through a low impedance connection. if an analog ground path is available in the application pcb (printed circuit board), it is highly recommended that the v ss pin be tied to the analog ground path or isolated within an analog ground plane of the circuit board. 3.3 serial data pin (sda) sda is the serial data pin of the i 2 c interface. the sda pin is used to write or read the dac register and eeprom data. the sda pin is an open-drain n-chan nel driver. therefore, it needs a pull-up resistor from the v dd line to the sda pin. except for start and stop conditions, the data on the sda pin must be stable during the high period of t he clock. the high or low state of the sda pin can only change when the clock signal on the scl pin is low. refer to section 7.0 ?i 2 c serial interface communication? for more details of i 2 c serial interface communication. 3.4 serial clock pin (scl) scl is the serial clock pin of the i 2 c interface. the mcp4725 acts only as a slave and the scl pin accepts only external serial clocks. the input data from the master device is shifted into the sda pin on the rising edges of the scl clock and output from the mcp4725 occurs at the falling edges of the scl clock. the scl pin is an open-drain n-channel driver. therefore, it needs a pull-up resistor from the v dd line to the scl pin. refer to section 7.0 ?i 2 c serial interface com- munication? for more details of i 2 c serial interface communication. 3.5 device address selection pin (a0) this pin is used to select the a0 address bit by the user. the user can tie this pin to v ss (logic ? 0 ?), or v dd (logic ? 1 ?), or can be actively driven by the digital logic levels, such as the i 2 c master output. see section 7.2 ?device addressing? for more details of the address bits. table 3-1: pin function table mcp4725 name description sot-23 1v out analog output voltage 2v ss ground reference 3v dd supply voltage 4sdai 2 c serial data 5scli 2 c serial clock input 6a0i 2 c address bit selection pin (a0 bit). this pin can be tied to v ss or v dd , or can be actively driven by the digital logic levels. the logic state of this pin determines what the a0 bit of the i 2 c address bits should be. mcp4725 ds22039d-page 14 ? 2009 microchip technology inc. notes: ? 2009 microchip technology inc. ds22039d-page 15 mcp4725 4.0 terminology 4.1 resolution the resolution is the number of dac output states that divide the full scale range. for the 12-bit dac, the resolution is 2 12 or the dac code ranges from 0 to 4095. 4.2 lsb the least significant bit or the ideal voltage difference between two successive codes. equation 4-1: 4.3 integral nonlinearity (inl) or relative accuracy inl error is the maximum deviation between an actual code transition point and its corresponding ideal transition point (straight line). figure 2-5 shows the inl curve of the mcp4725. the end-point method is used for the calculation. the inl error at a given input dac code is calculated as: equation 4-2: figure 4-1: inl accuracy. 4.4 differential nonlinearity (dnl) differential nonlinearity error ( figure 4-2 ) is the measure of step size between codes in actual transfer function. the ideal step si ze between codes is 1 lsb. a dnl error of zero would imply that every code is exactly 1 lsb wide. if the dnl error is less than 1 lsb, the dac guarantees monotonic output and no missing codes. the dnl error between any two adjacent codes is calculated as follows: equation 4-3: lsb ideal v ref 2 n ------------ - v full scale v zero scale ? () 2 n 1 ? ------------------------------------------------------------------ = = where: v ref = the reference voltage = v dd in the mcp4725. this v ref is the ideal full scale voltage range n = the number of digital input bits. (n = 12 for mcp4725) inl v out v ideal ? () lsb --------------------------------------- = where: v ideal = code*lsb v out = the output voltage measured at the given input code 010 001 000 analog output (lsb) dac input code 011 111 100 101 1 2 3 4 5 6 0 7 110 ideal transfer function actual transfer function inl = < -1 lsb inl = 0.5 lsb inl = - 1 lsb dnl v out lsb ? lsb ---------------------------------- = where: v out = the measured dac output voltage difference between two adjacent input codes. mcp4725 ds22039d-page 16 ? 2009 microchip technology inc. figure 4-2: dnl accuracy. 4.5 offset error offset error ( figure 4-3 ) is the deviation from zero volt- age output when the digital input code is zero. this error affects all codes by the same amount. in the mcp4725, the offset error is not trimmed at the factory. however, it can be calibrated by software in application circuits. figure 4-3: offset error. 4.6 gain error gain error (see figure 4-4 ) is the difference between the actual full scale output voltage from the ideal output voltage on the transfer curve. the gain error is calculated after nullifying the offset error, or full scale error minus the offset error. the gain error indicates how well the slope of the actual transfer function matches the slope of the ideal transfer function. the gain error is usually expressed as percent of full scale range (% of fsr) or in lsb. in the mcp4725, the gain erro r is not calibrated at the factory and most of the gain error is contributed by the output op amp saturation near the code range beyond 4000. for the applications which need the gain error specification less than 1% maximum, the user may consider using the dac code range between 100 and 4000 instead of using full code range (code 0 to 4095). the dac output of the code range between 100 and 4000 is much linear than full scale range (0 to 4095). the gain error can be calibrated by software in applications. 4.7 full scale error (fse) full scale error ( figure 4-4 ) is the sum of offset error plus gain error. it is the difference between the ideal and measured dac output voltage with all bits set to one (dac input code = fffh). equation 4-4: figure 4-4: gain error and full scale error. 4.8 gain error drift gain error drift is the variat ion in gain error due to a change in ambient temperatur e. the gain error drift is typically expressed in ppm/ o c. 010 001 000 analog output (lsb) dac input code 011 111 100 101 1 2 3 4 5 6 0 7 dnl = 2lsb dnl = 0.5 lsb 110 ideal transfer function actual transfer function analog output ideal transfer function actual transfer function dac input code 0 offset error fse v out v ideal ? () lsb --------------------------------------- = where: v ideal =(v ref ) (1 - 2 -n ) - v offset v ref = the reference voltage. v ref = v dd in the mcp4725 analog output actual transfer function actual transfer function dac input code 0 gain error ideal transfer function after offset error removed full scale error ? 2009 microchip technology inc. ds22039d-page 17 mcp4725 4.9 offset error drift offset error drift is the variation in offset error due to a change in ambient temperature. the offset error drift is typically expressed in ppm/ o c. 4.10 settling time the settling time is the time delay required for the dac output to settle to its new output value from the start of code transition, within specified accuracy. in the mcp4725, the settling time is a measure of the time delay until the dac output reaches its final value (within 0.5 lsb) when the dac code changes from 400h to c00h. 4.11 major-code transition glitch major-code transition glitch is the impulse energy injected into the dac analog output when the code in the dac register changes state. it is normally specified as the area of the glitch in nv-sec. and is measured when the digital code is changed by 1 lsb at the major carry transition (example: 011...111 to 100... 000, or 100... 000 to 011 ... 111). 4.12 digital feedthrough digital feedthrough is the glitch that appears at the analog output caused by coupling from the digital input pins of the device. it is specified in nv-sec. and is measured with a full scale change on the digital input pins (example: 000... 000 to 111... 111, or 111... 111 to 000... 000). the digital feedthrough is measured when the dac is not being written to the register. mcp4725 ds22039d-page 18 ? 2009 microchip technology inc. notes: ? 2009 microchip technology inc. ds22039d-page 19 mcp4725 5.0 general description the mcp4725 is a single channel buffered voltage output 12-bit dac with non-volatile memory (eeprom). the user can st ore configuration register bits (2 bits) and dac input data (12 bits) in non-volatile eeprom (14 bits) memory. when the device is powered on first, it loads the dac code from the eeprom and outputs the analog output accordingly with the programmed settings. the user can reprogram the eeprom or dac register any time. the device uses a resistor string architecture. dac?s output is buffered with a low power precision amplifier. this output amplifier provides low offset voltage and low noise, as well as rail-to-rail output. the amplifier can also provide high source currents (v out pin to v ss ). the dac can be configured to normal or power saving power-down mode by setting the configuration register bits. the device uses a two-wire i 2 c compatible serial interface and operates from a single power supply ranging from 2.7v to 5.5v. 5.1 output voltage the input coding to the mcp4725 device is unsigned binary. the output voltage range is from 0v to v dd . the output voltage is given in equation 5-1 : equation 5-1: 5.1.1 output amplifier the dac output is buffered with a low-power, precision cmos amplifier. this amp lifier provides low offset voltage and low noise. the output stage enables the device to operate with output voltages close to the power supply rails. refer to section 1.0 ?electrical characteristics? for range and load conditions. the output amplifier can drive the resistive and high capacitive loads without osc illation. the amplifier can provide maximum load current as high as 25 ma which is enough for most of a programmable voltage reference applications. 5.1.2 driving resistive and capacitive loads the mcp4725 output stage is capable of driving loads up to 1000 pf in parallel with 5 k ? load resistance. figure 2-15 shows the v out vs. resistive load. v out drops slowly as the load resistance decreases after about 3.5 k ? . 5.2 lsb size one lsb is defined as the ideal voltage difference between two successive codes. (see equation 4-1 ). table 5-1 shows an example of the lsb size over full scale range (v dd ). table 5-1: lsb sizes for mcp4725 (example) 5.3 voltage reference the mcp4725 device uses the v dd as its voltage reference. any variation or noises on the v dd line can affect directly on the dac output. the v dd needs to be as clean as possible for accurate dac performance. 5.4 reset conditions in the reset conditions, the device uploads the eeprom data into the dac register. the device can be reset by two independent events: (a) by por or (b) by i 2 c general call reset command. the factory defaul t settings for the eeprom prior to shipment are shown in ta b l e 5 - 3 (set for a middle scale output). the user can rewrit e or read the dac register or eeprom anytime after the power-on-reset event. 5.4.1 power-on-reset the device?s internal po wer-on-reset (por) circuit ensures that the device powers up in a defined state. if the power supply voltage is less than the por thresh- old (v por = 2v, typical), all circuits are disabled and there will be no dac output. when the v dd increases above the v por , the device takes a reset state. during the reset period, the device uploads all configuration and dac input c odes from eeprom. the dac output will be the same as for the value last stored in the eeprom. this enables the device returns to the same state that it was at the la st write to the eeprom before it was powered off. v out v ref d n () 4096 ------------------------------ - = where: v ref =v dd d n = input code full scale range (v dd ) lsb size condition 3.0v 0.73 mv 3v / 4096 5.0v 1.22 mv 5v / 4096 mcp4725 ds22039d-page 20 ? 2009 microchip technology inc. 5.4.2 v dd ramp rate and eeprom the mcp4725 uploads the eeprom data to the dac register during power-up se quence. however, if the v dd ramp rate is too slow ( <1 v/ms), the device may not be able to load the eeprom data to the dac register. therefore, the dac output that is correspond- ing to the current eeprom data may not available to the output pin. it is highly recommended to send a gen- eral call reset command (see section 7.3.1 ?gen- eral call reset? ) after power-up. this command will reset the device at a stable v dd and make the dac out- put available immediately using the eeprom data. 5.5 normal and power-down modes the device has two modes of operation: normal mode and power-down mode. the mode is selected by programming the power-down bits (pd1 and pd0) in the configuration register. the user can also program the two power-down bits in non-volatile eeprom memory. when the normal mode is selected, the device operates a normal digital-to-analog conversion. if the power-down mode is selected, the device enters a power saving condition by shutting down most of the internal circuits. during the power-down mode, all internal circuits except the i 2 c interface are disabled and there is no data conversion event, and no v out is available. the device also switches the output stage from the output of the amplifier to a known resistive load. the value of the resistive load is determined by the state of the power-down bits (pd1 and pd0). table 5-2 shows the outcome of the power-down bit and the resistive load. during the power-down mode, the device draws about 60 na (typical). although most of internal circuits are shutdown, the serial interface remains active in order to receive the i 2 c command. the device exits the power-down mode immediately when (a) it receives a ne w write command for normal mode or (b) it receives an i 2 c general call wake-up command. when the dac operation mode is changed from power-down to normal mode, the output settling time takes less than 10 s, but greater than the standard active mode settling time (6 s, typical). table 5-2: power-down bits figure 5-1: output stage for power- down mode. pd1 pd0 function 00 normal mode 01 1k ? resistor to ground (1) 10 100 k ? resistor to ground (1) 11 500 k ? resistor to ground (1) note 1: in the power-down mode: v out is off and most of internal circuits are disabled. 1k ? 100 k ? 500 k ? power-down control circuit resistive load v out op amp resistive string dac ? 2009 microchip technology inc. ds22039d-page 21 mcp4725 5.6 non-volatile eeprom memory the mcp4725 device has a 14-bit wide eeprom memory to store configuration bit (2 bits) and dac input data (12 bits). these bits are readable and re- writable with i 2 c interface commands. the device has an on-chip charge pump circuit to write the eeprom memory bits without using an external program voltage. the eeprom writing operation is initiated when the device receives an eeprom write command (c2 = 0, c1 = 1, c0 = 1). the configuration and writing data bits are transferred to the eeprom memory block. a status bit, rdy/bsy , stays low during the eeprom writing and goes high as the write operation is completed. while the rdy/bsy bit is low (during the eeprom writing), any new write command is ignored (for eeprom or dac register). ta b l e 5 - 3 shows the eeprom bits and factor y default settings. table 5-4 shows the dac input register bits of the mcp4725. table 5-4: dac register table 5-3: eeprom memory an d factory default settings (total number of bits: 14 bits) bit name pd1 pd0 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 bit function power-down select (2 bits) dac input data (12 bits) factory default value 00 (1) 1 (2) 00000000000 note 1: see table 5-2 for details. 2: bit d11 = ?1? (while all other bits are ? 0 ?) enables the device to output 0.5 * v dd (= middle scale output). bit name c2 c1 c0 rdy/ bsy porpd1pd0d11d10d9d8d7d6d5d4d3d2d1d0 bit function command type (1) power- down select data (12 bits) note 1: write eeprom status indication bi t (0:eeprom write is not complete d. 1:eeprom write is complete.) mcp4725 ds22039d-page 22 ? 2009 microchip technology inc. notes: ? 2009 microchip technology inc. ds22039d-page 23 mcp4725 6.0 theory of operation when the device is connected to the i 2 c bus line, the device is working as a slave device. the master (mcu) can write/read the dac in put register or eeprom using the i 2 c interface command. the mcp4725 device address contains four fixed bits ( 1100 = device code) and three address bits (a2, a1, a0). the a2 and a1 bits are hard-wired during manufacturing, and a0 bit is determined by the logic state of a0 pin. the a0 pin can be connected to v dd or v ss , or actively driven by digital logic levels. the following sections describe the communication protocol to send or read the data code and write/read the eeprom using the i 2 c interface. see section 7.0 ?i 2 c serial interface communication? . 6.1 write commands the write commands are used to load the configuration bits and dac input code to t he dac register, or to write to the eeprom of the dev ice. the write command types are defined by using three write command type bits (c2, c1, c0). ta b l e 6 - 2 shows the write command types and their functions. there are three command types for the mcp4725. the four ?reserved? commands in table 6-2 are for future use. the mcp4725 ignores the ?reserved? commands. write command protocol examples are shown in figure 6-1 and figure 6-2 . the input data code is coded as shown in ta b l e 6 - 1 . the msb of the data is always transmitted first and the format is unipolar binary. table 6-1: input data coding 6.1.1 write command for fast mode (c2 = 0, c1 = 0, c0 = x, x = don?t care) the fast write command is used to update the dac register. the data in the eepr om of the device is not affected by this command. this command updates power-down mode selection bits (pd1 and pd0) and 12 bits of the dac input code in the dac register. figure 6-1 shows an example of the fast write command for the mcp4725 device. 6.1.2 write command for dac input register (c2 = 0, c1 = 1, c0 = 0) in mcp4725, this command performs the same function as the fast mode command in section 6.1.1 ?write command for fast mode (c2 = 0, c1 = 0, c0 = x, x = don?t care)? . figure 6-2 shows the write command protocol for the mcp4725. as shown in figure 6-2 , the d11 - d0 bits in the third and fourth bytes are dac input data. the last 4 bits (x, x, x, x) in the fourth byte are don?t care bits. the device executes the master?s write command after receiving the last byte (4th byte). the master can send a stop bit to terminate the current sequence, or send a repeated start bit followed by an address byte. if the device receives three data bytes continuously after the 4th byte, it updates fr om the 2nd to the 4th data bytes with the last three input data bytes. the contents of the register are updated at the end of the 4th byte. the device ignores any partially received data bytes if the i 2 c communication with the master ends before completing the 4th byte. 6.1.3 write command for dac input register and eeprom (c2 = 0, c1 = 1, c0 = 1) when the device receives th is command, it (a) loads the configuration and data bits to the dac register, and (b) also writes the eepr om. when the device is writing the eeprom, the rdy/bsy bit goes low and stays low until the eepr om write operation is completed. the state of the rdy/bsy bit can be monitored by a read command. figure 6-2 shows the details of the this write command protocol and figure 6-3 shows the details of the read command. input code nominal output voltage (v) 111111111111 (fffh) v dd - 1 lsb 111111111110 (ffeh) v dd - 2 lsb 000000000010 (002h) 2 lsb 000000000001 (001h) 1 lsb 000000000000 (000h) 0 mcp4725 ds22039d-page 24 ? 2009 microchip technology inc. table 6-2: write command type figure 6-1: fast mode write command. c 2 c 1 c0 command name function 0 0 x fast mode this command is used to change the dac register. eeprom is not affected 00x ? ? 0 1 0 write dac register load configuration bits and data code to the dac register 0 1 1 write dac register and eeprom (a) load configuration bits and data code to the dac register and (b) also write the eeprom 1 0 0 reserved reserved for future use 1 0 1 reserved reserved for future use 1 1 0 reserved reserved for future use 1 1 1 reserved reserved for future use note 1: x = dont? care. fast mode does not use c0 bit. 2: the mcp4725 ignores the ?reserved? commands. 1st byte (device addressing) device code address r/w ack (mcp4725) 2nd byte 3rd byte dac register data (12 bits) ack (mcp4725) repeat bytes of 2nd and 3rd bytes write dac register using fast mode write command: (c2, c1) = (0, 0) fast mode command (c2, c1 = 0, 0) ack (mcp4725) power down select start bit 2nd byte 3rd byte read/write command stop bit stop bit see note 1 see note 2 ack (mcp4725) see note 2 note 1: a2 and a1 bits are programmed at the factory by hard -wired, and a0 bit is determined by the logic state of a0 pin. 2: the device updates v out at the falling edge of the ack pulse of the 3rd byte. 1100a2 0 a1 a0 0 0 pd1 pd0 d11 d8 d10 d9 d7 d6 d5 d4 d3 d0 d2 d1 0 0 pd1 pd0 d11 d8 d10 d9 d7 d6 d5 d4 d3 d0 d2 d1 bits ack (mcp4725) ? 2009 microchip technology inc. ds22039d-page 25 mcp4725 figure 6-2: write commands for dac in put register and eeprom. (a) write dac register: (c 2, c1, c0) = (0,1,0) or (b) write dac register and e eprom: (c2, c1, c0) = (0,1,1) 1st byte (device addressing) ack (mcp4725) 2nd byte 3rd byte ack (mcp4725) 4th byte d3 d2 d0 d1 1 1 0 0 a2 a1 a0 0 c2 c1 c0 x x pd1 pd0 x x x x x d11 d10 d9 d8 d7 d6 d5 d4 start bit dac register data (12 bits) stop bit power down selection unused unused unused device code address bits r/w write command type: write dac register: (c2 = 0, c1 = 1, c0 = 0) write dac register and eeprom: (c 2 = 0, c1 = 1, c0 = 1). see note 1 ? the device updates the v out after this ack pulse is issued. ? for eeprom write: - the charge pump initiates the eeprom writing sequence at the falling edge of this ack pulse. - the rdy/bsy bit (pin) goes ?low? at the falling edge of this ack pulse and back to ?high? immediately after the eeprom write is completed. ack (mcp4725) 2nd byte 3rd byte ack (mcp4725) 4th byte d3 d2 d0 d1 c2 c1 c0 x x pd1 pd0 x x x x x d11 d10 d9 d8 d7 d6 d5 d4 stop bit repeat bytes of 2nd - 4th bytes note 1: rdy/bsy bit stays ?low? during the eeprom write. any new write command including repeat bytes during the eeprom write mode is ignored. the rdy/bsy bit sets to ?high? after the eeprom write is completed. mcp4725 ds22039d-page 26 ? 2009 microchip technology inc. 6.2 read command if the r/w bit is set to a logic ?high?, then the device outputs on sda pin, the dac register and eeprom data. figure 6-3 shows an example of reading the register and eeprom dat a. the 2nd byte in figure 6- 3 indicates the current condition of the device operation. the rdy/bsy bit indicates eeprom writing status. the rdy/bsy bit stays low during eeprom writng and high when the writing is completed. figure 6-3: read command and output data format. 1st byte ack (mcp4725) 2nd byte 3rd byte ack (master) 4th byte d3 d2 d0 d1 1 1 0 0 a2 a1 a0 1 rdy/ xxxpd1pd0x xxxx d11 d10 d9 d8 d7 d6 d5 d4 start bit device code address bits r/w 5th byte 6th byte d7 d6 d4 d5 d3 d2 d1 d0 x pd1 pd0 x d11 d10 d9 d8 stop bit note 1: bytes 2 - 6 are repeated in repeat bytes after byte 6. 2: x is don?t care bit. read command dac register data (12 bits) in dac register current settings see note 2 eeprom write status indicate bit (1: completed, 0: incomplete) bsy eeprom data por ack (master) ack (master) ? 2009 microchip technology inc. ds22039d-page 27 mcp4725 7.0 i 2 c serial interface communication 7.1 overview the mcp4725 device uses a two-wire i 2 c serial interface that can operate on a standard, fast or high speed mode. a device that sends data onto the bus is defined as transmitter, and a device receiving data as receiver. the bus has to be controlled by a master device which generates the serial clock (scl), controls the bus access and generates the start and stop conditions. the mcp4725 device works as slave. both master and slave can operate as transmitter or receiver, but the master device determines which mode is activated. an exampl e of hardware connection diagram is shown in figure 8-1 . communication is initiated by the master (m icrocontroller) which sends the start bit, followed by the slave address byte. the first byte transmitted is always the slave address byte, which contains the device code, the address bits, and the r/w bit. the device code for the mcp4725 device is 1100 . when the device receives a read command (r/w = 1 ), it transmits the contents of the dac input register and eeprom. a non-acknowledge (nak) or repeated start bit can be transmitted at any time. see figure 6-3 for the read operation example. if writing to the device (r/w = 0 ), the device will expect write com- mand type bits in the following byte. see figure 6-1 and figure 6-2 for the write operation examples. the mcp4725 supports all three i 2 c operating modes: ? standard mode: bit rates up to 100 kbit/s ? fast mode: bit rates up to 400 kbit/s ? high speed mode (hs mode): bit rates up to 3.4 mbit/s refer to the phillips i 2 c document for more details of the i 2 c specifications. 7.2 device addressing the address byte is the first byte received following the start condition from the master device. the first part of the address byte consists of a 4-bit device code which is set to 1100 for the mcp4725. the device code is followed by three address bits (a2, a1, a0) which are programmed as follows: ? the choice of a2 and a1 bits are provided by the customer as part of th e ordering process. these bits are then programmed (hard-wired) during manufacturing ? the a2 and a1 are programmed to ? 00 ? (default), if not requested by customer ? a0 bit is determined by the logic state of a0 pin. the a0 pin can be tied to v dd or v ss , or can be actively driven by digital logic levels. the advantage of using the a0 pin is that the users can control the a0 bit on their application pcb circuit and also two identical mcp4725 devices can be used on the same bus line. when the device receives an address byte, it compares the logic state of the a0 pin with the a0 address bit received before responding with the acknowledge bit. the logic state of the a0 pin needs to be set prior to the interface communication. figure 7-1: device addressing. start bit read/write bit address byte r/w ack acknowledge bit slave address 1 1 0 0 slave address for mcp4725 a2 a1 a0 note: a2 and a1: programmed (hard-wired) at the factory. please contact microchip technology inc. for a2 and a1 programming options. a0: use the logic level state of a0 pin. device code address bits mcp4725 ds22039d-page 28 ? 2009 microchip technology inc. 7.3 general call the mcp4725 device acknowledges the general call address (0x00 in the first byte). the meaning of the general call address is always specified in the second byte (see figure 7-2 ). the i 2 c specification does not allow to use ?00000000? (00h) in the second byte. please refer to the phillips i 2 c document for more details of the general call specifications. the mcp4725 supports the following general calls: 7.3.1 general call reset the general reset occurs if the second byte is ? 00000110 ? (06h). at the ackn owledgement of this byte, the device will abort current conversion and perform an internal reset si milar to a power-on-reset (por). immediately after this reset event, the device uploads the contents of the eeprom into the dac register. 7.3.2 general call wake-up if the second byte is ? 00001001 ? (09h), the device will reset the power-down bits. after receiving this com- mand, the power-down bits of the dac register are set to a normal operation (pd1, pd2 = 0,0). the power- down bit settings in eeprom are not affected. figure 7-2: general call address format. 7.4 high-speed (hs) mode the i 2 c specification requires that a high-speed mode device must be ?activated? to operate in high-speed (3.4 mbit/s) mode. this is done by sending a special address byte of 00001xxx following the start bit. the xxx bits are unique to the high-speed (hs) mode master. this byte is referred to as the high-speed (hs) master mode code (hsmmc). the mcp4725 device does not acknowledge this byte. however, upon receiving this command, the device switches to hs mode and can communicate at up to 3.4 mbit/s on sda and scl lines. the device will switch out of the hs mode on the next stop condition. for more information on the hs mode, or other i 2 c modes, please refer to the phillips i 2 c specification. 7.5 i 2 c bus characteristics the i 2 c specification defines the following bus protocol: ? data transfer may be in itiated only when the bus is not busy. ? during data transfer, the data line must remain stable whenever the clock line is high. changes in the data line while the clock line is high will be interpreted as a start or stop condition. accordingly, the following bus conditions have been defined using figure 7-3 . 7.5.1 bus not busy (a) both data and clock lines remain high. 7.5.2 start data transfer (b) a high to low transition of the sda line while the clock (scl) is high determines a start condition. all commands must be preceded by a start condition. 7.5.3 stop data transfer (c) a low to high transition of the sda line while the clock (scl) is high determines a stop condition. all operations must be ended with a stop condition. 7.5.4 data valid (d) the state of the data line represents valid data when, after a start condition, the data line is stable for the duration of the high period of the clock signal. the data on the line must be changed during the low period of the clock signal. there is one clock pulse per bit of data. each data transfer is init iated with a start condition and terminated with a stop condition. lsb first byte ack x 0 0 0 0 0 0 0 0 a a x x x x x x x (general call address ) second byte ack ? 2009 microchip technology inc. ds22039d-page 29 mcp4725 7.5.5 acknowledge each receiving device, when addressed, is obliged to generate an acknowledge after the reception of each byte. the master device must generate an extra clock pulse which is associated with this acknowledge bit. the device that acknowledges, has to pull down the sda line during the acknowledge clock pulse in such a way that the sda line is stable low during the high period of the acknowledge related clock pulse. of course, setup and hold times must be taken into account. during reads, a master must send an end of data to the slave by not generating an acknowledge bit on the last byte that has been clocked out of the slave. in this case, the slave (mcp4725) will leave the data line high to enable the master to generate the stop condition. figure 7-3: data transfer sequence on the serial bus. scl sda (a) (b) (d) (d) (a) (c) start condition address or acknowledge valid data allowed to change stop condition mcp4725 ds22039d-page 30 ? 2009 microchip technology inc. table 7-1: i 2 c serial timing specifications electrical specifications: unless otherwise specified, all limits are specified for t a = -40 to +85c, v dd = +2.7v to +5.0v, v ss = 0v. parameters sym min typ max units conditions standard mode clock frequency f scl 0 ? 100 khz clock high time t high 4000 ? ? ns clock low time t low 4700 ? ? ns sda and scl rise time t r ? ? 1000 ns from v il to v ih (note 1) sda and scl fall time t f ? ? 300 ns from v ih to v il (note 1) start condition hold time t hd:sta 4000 ? ? ns after this period, the first clock pulse is generated. (repeated) start condition setup time t su:sta 4700 ? ? ns data hold time t hd:dat 0 ? 3450 ns note 3 data input setup time t su:dat 250 ? ? ns stop condition setup time t su:sto 4000 ? ? ns output valid from clock t aa 0 ? 3750 ns notes 2 and 3 bus free time t buf 4700 ? ? ns time between start and stop conditions. fast mode clock frequency t scl 0 ? 400 khz clock high time t high 600 ? ? ns clock low time t low 1300 ? ? ns sda and scl rise time t r 20 + 0.1cb ? 300 ns from v il to v ih (note 1) sda and scl fall time t f 20 + 0.1cb ? 300 ns from v ih to v il (note 1) start condition hold time t hd:sta 600 ? ? ns after this period, the first clock pulse is generated (repeated) start condition setup time t su:sta 600 ? ? ns data hold time t hd:dat 0 ? 900 ns note 4 data input setup time t su:dat 100 ? ? ns stop condition setup time t su:sto 600 ? ? ns output valid from clock t aa 0 ? 1200 ns notes 2 and 3 bus free time t buf 1300 ? ? ns time between start and stop conditions. note 1: this parameter is ensured by characterization and not 100% tested. 2: this specification is not a part of t he i2c specification. this specification is equi valent to the data hold time ( t hd:dat ) plus sda fall (or rise) time: t aa = t hd:dat + t f ( or t r ). 3: if this parameter is too short, it can create an unintended st art or stop condition to other devices on the same bus line. if this parameter is too long, clock low time (t low ) can be affected. 4: for data input: this parameter must be longer than t sp . if this parameter is too long, the data input setup (t su:dat ) or clock low time (t low ) can be affected. for data output: this parameter is charac terized, and tested indirectly by testing t aa parameter. 5: all timing parameters in high-speed modes are tested at v dd = 5v. ? 2009 microchip technology inc. ds22039d-page 31 mcp4725 high speed mode (note 5) clock frequency f scl 0?3.4mhzc b = 100 pf 0?1.7mhzc b = 400 pf clock high time t high 60 ? ? ns c b = 100 pf, f scl = 3.4 mhz 120 ? ? ns c b = 400 pf, f scl = 1.7 mhz clock low time t low 160 ? ? ns c b = 100 pf, f scl = 3.4 mhz 320 ? ? ns c b = 400 pf, f scl = 1.7 mhz scl rise time (note 1) t r:scl ? ? 40 ns from v il to v ih , c b = 100 pf, f scl = 3.4 mhz ? ? 80 ns from v il to v ih , c b = 400 pf, f scl = 1.7 mhz scl fall time (note 1) t f:scl ? ? 40 ns from v ih to v il , c b = 100 pf, f scl = 3.4 mhz ? ? 80 ns from v ih to v il , c b = 400 pf, f scl = 1.7 mhz sda rise time (note 1) t r: dat ? ? 80 ns from v il to v ih , c b = 100 pf, f scl = 3.4 mhz ? ? 160 ns from v il to v ih , c b = 400 pf, f scl = 1.7 mhz sda fall time (note 1) t f: dat ? ? 80 ns from v ih to v il , c b = 100 pf, f scl = 3.4 mhz ? ? 160 ns from v ih to v il , c b = 400 pf, f scl = 1.7 mhz data hold time (note 4) t hd:dat 0 ? 70 ns c b = 100 pf, f scl = 3.4 mhz 0 ? 150 ns c b = 400 pf, f scl = 1.7 mhz output valid from clock (notes 2 and 3) t aa ? ? 150 ns c b = 100 pf, f scl = 3.4 mhz ? ? 310 ns c b = 400 pf, f scl = 1.7 mhz start condition hold time t hd:sta 160 ? ? ns after this period, the first clock pulse is generated start (repeated) condition setup time t su:sta 160 ? ? ns data input setup time t su:dat 10 ? ? ns stop condition setup time t su:sto 160 ? ? ns table 7-1: i 2 c serial timing specifications (continued) electrical specifications: unless otherwise specified, all limits are specified for t a = -40 to +85c, v dd = +2.7v to +5.0v, v ss = 0v. parameters sym min typ max units conditions note 1: this parameter is ensured by characterization and not 100% tested. 2: this specification is not a part of t he i2c specification. this specification is equi valent to the data hold time ( t hd:dat ) plus sda fall (or rise) time: t aa = t hd:dat + t f ( or t r ). 3: if this parameter is too short, it can create an unintended st art or stop condition to other devices on the same bus line. if this parameter is too long, clock low time (t low ) can be affected. 4: for data input: this parameter must be longer than t sp . if this parameter is too long, the data input setup (t su:dat ) or clock low time (t low ) can be affected. for data output: this parameter is charac terized, and tested indirectly by testing t aa parameter. 5: all timing parameters in high-speed modes are tested at v dd = 5v. mcp4725 ds22039d-page 32 ? 2009 microchip technology inc. figure 7-4: i 2 c bus timing data. t f scl sda t su:sta t sp t hd:sta t low t high t hd:dat t aa t su:dat t r t su:sto t buf 0.3v dd 0.7v dd ? 2009 microchip technology inc. ds22039d-page 33 mcp4725 8.0 typical applications the mcp4725 device is one of microchip?s latest dac device family with non-vol atile eeprom memory. the device is a general purpose resistive string dac intended to be used in applications where a precision, and low power dac with moderate bandwidth is required. since the device includes non-volatile eeprom memory, the user can use this device for applications that require the output to re turn to the previous set-up value on subsequent power-ups. applications generally suited for the mcp4725 device family include: ? set point or offset trimming ? sensor calibration ? portable instrumentation (battery powered) ? motor speed control 8.1 connecting to i 2 c bus using pull-up resistors the scl and sda pins of the mcp4725 are open-drain configurations. these pins r equire a pull-up resistor as shown in figure 8-1 . the value of these pull-up resistors depends on the operating speed (standard, fast, and high speed) and loading capacitance of the i 2 c bus line. higher value of pull-up resistor consumes less power, but increases the signal transition time (higher rc time constant) on the bus. therefore, it can limit the bus operating speed. the lower resistor value, on the other hand, consumes higher power, but allows higher operating speed. if the bus line has higher capacitance due to long bus line or high number of devices connected to the bus, a smaller pull-up resistor is needed to compensate the long rc time constant. the pull-up resistor is typically chosen between 1 k ? and 10 k ? ranges for standard and fast modes, and less than 1 k ? for high speed mode. figure 8-1: i 2 c bus interface connection with a0 pin tied to v ss . two devices with the same a2 and a1 address bits can be connected to the same i 2 c bus by utilizing the a0 address pin (example: a0 pin of device a is tied to v dd , and the other device?s pin is tied to v ss ). 8.1.1 device connection test the user can test the presence of the mcp4725 on the i 2 c bus line without performing the data conversion. this test can be achieved by checking an acknowledge response from the mcp4725 after sending a read or write command. here is an example using figure 8-2 : (a) set the r/w bit ?high? in the address byte. (b) if the mcp4725 is connected to the i 2 c bus line, it will then acknowledge by pulling sda bus low during the ack clock and then release the bus back to the i 2 c master. (c) a stop or repeated start bit can then be issued from the master and i 2 c communication can continue. figure 8-2: i 2 c bus connection test. mcp4725 v out a0 scl v ss 1 2 3 4 5 6 v dd sda 10 f 0.1 f r r analog v dd v dd to m c u (master) output note 1: r is the pull-up resistor. typically 1 ~ 10 k ? 2: a0 can be tied to v ss , v dd or driven by mcu 123456789 scl sda 11 0 0a2a1a0 1 start bit address byte address bits device bits r/w start bit mcp4725 ack response mcp4725 ds22039d-page 34 ? 2009 microchip technology inc. 8.2 using non-volatile eeprom memory the user can store the dac input code (12 bits) and power-down configuration bits (2 bits) in the internal non-volatile eeprom memory using the i 2 c write command. the user can also read the eeprom data using the i 2 c read command. when the device is first powered after power is shut down, the device uploads the eeprom contents to the dac register automatically and provides the dac output immediately. this feature is very useful in applications where the dac device is used to provide set point or calibration data for other devices in the application system. the dac will not lose the important system operational paramete rs due to the system power failure incidents. see section 5.6 ?non-volatile eeprom memory? for more details of the non-volatile eeprom memory. 8.3 power supply considerations the power supply to the device is used for both v dd and dac reference voltage. any noise induced on the v dd line can affect on the dac performance. typical application will require a bypass capacitor in order to filter out high frequency noise on the v dd line. the noise can be induced onto t he power supply?s traces or as a result of changes on the dac output. the bypass capacitor helps to minimize the effect of these noise sources on signal integrity. figure 8-1 shows an example of using two bypass capacitors (a 10 f tantalum capacitor and a 0.1 f ceramic capacitor) in parallel on the v dd line. these capacitors should be placed as close to the v dd pin as possible (within 4mm). the power source should be as clean as possible. if the application circuit has separate digital and analog power supplies, the v dd and v ss pins of the mcp4725 should reside on the analog plane. 8.4 layout considerations inductively-coupled ac transients and digital switching noise from other devic es can affect on dac performance and dac output signal integrity. careful board layout will minimize these effects. bench testing has shown that a multi-layer board utilizing a low- inductance ground plane, isolated inputs, isolated outputs and proper decoupling are critical to achieving the performance that the mcp4725 is capable of providing. particularly harsh environments may require shielding of critical signals. separate digital and analog ground planes are recommended. in this case, the v ss pin and the ground pins of the v dd capacitors of the mcp4725 should be terminated to the analog ground plane. 8.5 application examples the mcp4725 is a rail-to-rail output dac designed to operate with a v dd range of 2.7v to 5.5v. its output amplifier is robust enough to drive common, small- signal loads directly, thus eliminating the cost and size of an external buffer for most applications. 8.5.1 dc set point or calibration a common application for the mcp4725 is a digitally- controlled set point or a calibration of variable parameters such as sensor offset or bias point. example 8-1 shows an example of the set point setting. since the mcp4725 is a 12-bit dac and uses the v dd supply as a reference source, it provides a v dd /4096 of resolution per step. ? 2009 microchip technology inc. ds22039d-page 35 mcp4725 8.5.2 decreasing the output step size calibrating the threshold of a diode, transistor or resistor may require a very small step size in the dac output voltage. these applications may require about 200 v of step resolution within 0.8v of range. one method of achieving this small step resolution is using a voltage divider at t he dac output. an example is shown in example 8-1 . the step size of the dac output is scaled down by the factor of the ratio of the voltage divider. note that the bypass capacitor on the output of the voltage divider plays a critical function in attenuating the output noise of the dac and the induced noise from the environment. example 8-1: set point or threshold calibration. to m c u (master) r r v dd comparator r 1 r 2 0.1 f v trip r sense mcp4725 v dd v out a0 scl v ss 1 2 3 4 5 6 v dd sda 10 f 0.1 f v dd dn input code (0 to 4095) = v out v dd dn 4096 ----------- - = v trip v out r 2 r 1 r 2 + ------------------- ?? ?? = light (ceramic) (tantalum) mcp4725 ds22039d-page 36 ? 2009 microchip technology inc. 8.5.3 building a ?window? dac some sensor applications require very high resolution around the set point or threshold voltage. example 8-2 shows an example of creating a ?window? around the threshold using a voltage divider network with a pull-up and pull-down resistor. in the circuit, the output voltage range is scaled down, but its step resolution is increased greatly. example 8-2: single-supply ?window? dac. v trip r 1 r 2 0.1 f comparator r 3 v cc- where: dn = dac input code (0 ? 4095) v cc+ v cc+ v cc- v out v out v dd dn 2 12 ------- = r 23 r 2 r 3 r 2 r 3 + ------------------- = v 23 v cc+ r 2 () v cc- r 3 () + r 2 r 3 + ------------------------------------------------------ = v trip v out r 23 v 23 r 1 + r 2 r 23 + -------------------------------------------- - = r 1 r 23 v 23 v out v o thevenin equivalent r sense to m c u (master) r r mcp4725 v dd v out a0 scl v ss 1 2 3 4 5 6 v dd sda 10 f 0.1 f v dd ? 2009 microchip technology inc. ds22039d-page 37 mcp4725 8.5.4 bipolar operation bipolar operation is achievable using the mcp4725 by using an external operational amplifier (op amp). this allows a general purpose dac, with its cost and availability advantages, to meet almost any desired output voltage range, power and noise performance. example 8-3 illustrates a simple bipolar voltage source configuration. r 1 and r 2 allow the gain to be selected, while r 3 and r 4 shift the dac's output to a selected offset. note that r 4 can be tied to v dd (= v ref ) instead of v ss , if a higher offset is desired. note that a pull-up to v dd could be used, instead of r 4 , if a higher offset is desired. example 8-3: digitally-controlled bipolar voltage source. v dd v out r 3 r 4 r 2 r 1 v in + 0.1 f v cc + v cc ? v in+ v out r 4 r 3 r 4 + -------------------- = v o v o v in+ 1 r 2 r 1 ----- - + ?? ?? v dd r 2 r 1 ----- - ?? ?? ? = to m c u (master) r r mcp4725 v dd v out a0 scl v ss 1 2 3 4 5 6 v dd sda 10 f 0.1 f v dd where: dn = dac input code (0 ? 4095) v out v dd dn 2 12 ------- = mcp4725 ds22039d-page 38 ? 2009 microchip technology inc. 8.5.4.1 design a bipolar dac using example 8-3 some applications desires an output step magnitude of 1 mv with an output range of 2.05v. the following steps explain the design solution: 1. calculate the range: +2.05v ? (-2.05v) = 4.1v. 2. calculate the resolution needed: 4.1v/1 mv = 4100 steps note that 2 12 = 4096 for 12-bit resolution. 3. the amplifier gain (r 2 /r 1 ), multiplied by v dd , must be equal to the desired minimum output to achieve bipolar operation. since any gain can be realized by choosing resistor values (r 1 +r 2 ), the v dd value must be selected first. if a v dd of 4.1v is used, solve for the amplifier?s gain by setting the dac code to 0, knowing that the out- put needs to be -2.05v. the equation can be simplified to : 4. next, solve for r 3 and r 4 by setting the dac to 4096, knowing that the output needs to be +2.05v. r 2 ? r 1 -------- - 2.05 ? v dd ------------- 2.05 ? 4.1 ------------- = = r 2 r 1 ----- - 1 2 -- - = if r 1 = 20 k ? and r 2 = 10 k ? , the gain will be 0.5. r 4 r 3 r 4 + () ----------------------- - 2.05v 0.5 v dd ? () + 1.5 v dd ? ------------------------------------------------ - 2 3 -- - == if r 4 = 20 k ? , then r 3 = 10 k ? ? 2009 microchip technology inc. ds22039d-page 39 mcp4725 8.5.5 programmable current source example 8-3 illustrates an example how to convert the dac voltage output to a digitally selectable current source by adding a voltage follower and a sensor register. figure 8-3: digitally controllabl e current source. load v dd i l i b r sense r r mcp4725 v dd v out a0 scl v ss 1 2 3 4 5 6 v dd sda 10 f 0.1 f v dd dn input code (0 to 4095) = i l v out r sense ------------------ 1 + ------------ - = v out v dd dn 4096 ----------- - = i b i l ---- = v out to m c u (master) mcp4725 ds22039d-page 40 ? 2009 microchip technology inc. notes: ? 2009 microchip technology inc. ds22039d-page 41 mcp4725 9.0 development support 9.1 evaluation & demonstration boards the mcp4725 sot-23-6 evaluation board is available from microchip technology in c. this board works with microchip?s pickit? serial analyzer. the user can program the dac input codes and eeprom data, or read the programmed data using the easy to use pickit serial analyzer with the graphic user interface software. refer to www.microchip.com for further information on this product?s capabilities and availability. figure 9-1: mcp4725 sot-23-6 evaluation board. figure 9-2: setup for the mcp4725 sot-23-6 evaluation b oard with pickit? serial analyzer. figure 9-3: example of pickit? serial user interface. usb cable to pc pickit serial mcp4725 sot-23-6 ev board dac analog output 1st write byte 2nd write byte 3rd write byte 4th write byte mcp4725 ds22039d-page 42 ? 2009 microchip technology inc. notes: ? 2009 microchip technology inc. ds22039d-page 43 mcp4725 10.0 packaging information 10.1 package marking information 1 6-lead sot-23 xxnn example 1 aj25 part number address option code mcp4725a0t-e/ch a0 (00) ajnn mcp4725a1t-e/ch a1 (01) apnn mcp4725a2t-e/ch a2 (10) aqnn mcp4725a3t-e/ch a3 (11) arnn legend: xx...x customer-specific information y year code (last digit of calendar year) yy year code (last 2 digits of calendar year) ww week code (week of january 1 is week ?01?) nnn alphanumeric traceability code pb-free jedec designator for matte tin (sn) * this package is pb-free. the pb-free jedec designator ( ) can be found on the outer packaging for this package. note : in the event the full microchip part nu mber cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. 3 e 3 e mcp4725 ds22039d-page 44 ? 2009 microchip technology inc. !! "# "$%" "& ! $%!! "& ! $%!!! $ ' " !" ! "$ #( ) *+, * ! ! $ ' $- % !..$%$$ ! /$ !$% $ 0 " . !1 ! ! $ 2 0 & $ $ " $ $$ ,33... 3 0 4$! 55 ## !5 $! 6 67 8 6% 9 &2! 6 2$ )*+ 7%$!" 5 "2$ *+ 7- : $ ; ) " "2 0 0 !! < ; $ "&& ; ) 7- ="$ # ; " "2 0 ="$ # ; < 7- 5 $ ; /$5 $ 5 ; /$ $ 5 ) ; < /$ > ; > 5 "0 !! < ; 5 "="$ 9 ; ) b e 4 n e1 pin1idby laser mark d 1 2 3 e e1 a a1 a2 c l l1 . + <* ? 2009 microchip technology inc. ds22039d-page 45 mcp4725 appendix a: revision history revision d (june 2009) the following is the list of modifications: 1. added v dd_ramp parameter in section ?electrical characteristics? and description in section 5.4.2 ?v dd ramp rate and eeprom? . revision c (november 2007) the following is the list of modifications: 1. corrected address options on product identification system page. revision b (october 2007) the following is the list of modifications: 1. added characterization graphs to document. 2. numerous edits throughout. 3. add new package marking address options. updated package marking information and package outline drawings. 4. added adress options to product identification system page. revision a (april 2007) ? original release of this document. mcp4725 ds22039d-page 46 ? 2009 microchip technology inc. notes: ? 2009 microchip technology inc. ds22039d-page 47 mcp4725 product identification system to order or obtain information, e.g., on pricing or de livery, refer to the factory or the listed sales office . device: mcp4725: single channel 12-bit dac w/eeprom memory address options: xx a2 a1 a0 a0 * = 0 0 external a1 = 0 1 external a2 = 1 0 external a3 = 1 1 external * default option. contact microchip factory for other address options tape and reel: t = tape and reel temperature range: e = -40c to +125c package: ch = plastic small outline transistor (sot-23-6), 6-lead examples: a) mcp4725a0t-e/ch: tape and reel, extended temp., 6ld sot-23 pkg. address option = a0 b) mcp4725a1t-e/ch: tape and reel, extended temp., 6ld sot-23 pkg. address option = a1 c) mcp4725a2t-e/ch: tape and reel, extended temp., 6ld sot-23 pkg. address option = a2 d) mcp4725a3t-e/ch: tape and reel, extended temp., 6ld sot-23 pkg. address option = a3 part no. x xx address temperature range device /xx package options x tape and reel mcp4725 ds22039d-page 48 ? 2009 microchip technology inc. notes: ? 2009 microchip technology inc. ds22039d-page 49 information contained in this publication regarding device applications and the like is prov ided only for your convenience and may be superseded by updates. it is your responsibility to ensure that your application me ets with your specifications. microchip makes no representations or warranties of any kind whether express or implied, written or oral, statutory or otherwise, related to the information, including but not limited to its condition, quality, performance, merchantability or fitness for purpose . microchip disclaims all liability arising from this information and its use. use of microchip devices in life support and/or safe ty applications is entirely at the buyer?s risk, and the buyer agrees to defend, indemnify and hold harmless microchip from any and all damages, claims, suits, or expenses resulting fr om such use. no licenses are conveyed, implicitly or ot herwise, under any microchip intellectual property rights. trademarks the microchip name and logo, th e microchip logo, dspic, k ee l oq , k ee l oq logo, mplab, pic, picmicro, picstart, rfpic and uni/o are registered trademarks of microchip technology incorporated in the u.s.a. and other countries. filterlab, hampshire, hi-tech c, linear active thermistor, mxdev, mxlab, seeval and the embedded control solutions company are register ed trademarks of microchip technology incorporated in the u.s.a. analog-for-the-digital age, a pplication maestro, codeguard, dspicdem, dspicdem.net, dspicworks, dsspeak, ecan, economonitor, fansense, hi-tide, in-circuit serial programming, icsp, icepic, mindi, miwi, mpasm, mplab certified logo, mplib, mplink, mtouch, nanowatt xlp, omniscient code generation, picc, picc-18, pickit, picdem, picdem.net, pictail, pic 32 logo, real ice, rflab, select mode, total endurance, tsharc, wiperlock and zena are trademarks of microc hip technology incorporated in the u.s.a. and other countries. sqtp is a service mark of mi crochip technology incorporated in the u.s.a. all other trademarks mentioned herein are property of their respective companies. ? 2009, microchip technology incorporated, printed in the u.s.a., all rights reserved. printed on recycled paper. note the following details of the code protection feature on microchip devices: ? microchip products meet the specification cont ained in their particular microchip data sheet. ? microchip believes that its family of products is one of the mo st secure families of its kind on the market today, when used i n the intended manner and under normal conditions. ? there are dishonest and possibly illegal meth ods used to breach the code protection fe ature. all of these methods, to our knowledge, require using the microchip pr oducts in a manner outside the operating specif ications contained in microchip?s data sheets. most likely, the person doing so is engaged in theft of intellectual property. ? microchip is willing to work with the customer who is concerned about the integrity of their code. ? neither microchip nor any other semiconduc tor manufacturer can guarantee the security of their code. code protection does not mean that we are guaranteeing the product as ?unbreakable.? code protection is constantly evolving. we at microchip are committed to continuously improving the code protection features of our products. attempts to break microchip?s c ode protection feature may be a violation of the digital millennium copyright act. if such acts allow unauthorized access to your softwa re or other copyrighted work, you may have a right to sue for relief under that act. microchip received iso/ts-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in chandler and tempe, arizona; gresham, oregon and design centers in california and india. the company?s quality system processes and procedures are for its pic ? mcus and dspic ? dscs, k ee l oq ? code hopping devices, serial eeproms, microperi pherals, nonvolatile memory and analog products. in addition, microchip?s quality system for the design and manufacture of development systems is iso 9001:2000 certified. ds22039d-page 50 ? 2009 microchip technology inc. americas corporate office 2355 west chandler blvd. chandler, az 85224-6199 tel: 480-792-7200 fax: 480-792-7277 technical support: http://support.microchip.com web address: www.microchip.com atlanta duluth, ga tel: 678-957-9614 fax: 678-957-1455 boston westborough, ma tel: 774-760-0087 fax: 774-760-0088 chicago itasca, il tel: 630-285-0071 fax: 630-285-0075 cleveland independence, oh tel: 216-447-0464 fax: 216-447-0643 dallas addison, tx tel: 972-818-7423 fax: 972-818-2924 detroit farmington hills, mi tel: 248-538-2250 fax: 248-538-2260 kokomo kokomo, in tel: 765-864-8360 fax: 765-864-8387 los angeles mission viejo, ca tel: 949-462-9523 fax: 949-462-9608 santa clara santa clara, ca tel: 408-961-6444 fax: 408-961-6445 toronto mississauga, ontario, canada tel: 905-673-0699 fax: 905-673-6509 asia/pacific asia pacific office suites 3707-14, 37th floor tower 6, the gateway harbour city, kowloon hong kong tel: 852-2401-1200 fax: 852-2401-3431 australia - sydney tel: 61-2-9868-6733 fax: 61-2-9868-6755 china - beijing tel: 86-10-8528-2100 fax: 86-10-8528-2104 china - chengdu tel: 86-28-8665-5511 fax: 86-28-8665-7889 china - hong kong sar tel: 852-2401-1200 fax: 852-2401-3431 china - nanjing tel: 86-25-8473-2460 fax: 86-25-8473-2470 china - qingdao tel: 86-532-8502-7355 fax: 86-532-8502-7205 china - shanghai tel: 86-21-5407-5533 fax: 86-21-5407-5066 china - shenyang tel: 86-24-2334-2829 fax: 86-24-2334-2393 china - shenzhen tel: 86-755-8203-2660 fax: 86-755-8203-1760 china - wuhan tel: 86-27-5980-5300 fax: 86-27-5980-5118 china - xiamen tel: 86-592-2388138 fax: 86-592-2388130 china - xian tel: 86-29-8833-7252 fax: 86-29-8833-7256 china - zhuhai tel: 86-756-3210040 fax: 86-756-3210049 asia/pacific india - bangalore tel: 91-80-3090-4444 fax: 91-80-3090-4080 india - new delhi tel: 91-11-4160-8631 fax: 91-11-4160-8632 india - pune tel: 91-20-2566-1512 fax: 91-20-2566-1513 japan - yokohama tel: 81-45-471- 6166 fax: 81-45-471-6122 korea - daegu tel: 82-53-744-4301 fax: 82-53-744-4302 korea - seoul tel: 82-2-554-7200 fax: 82-2-558-5932 or 82-2-558-5934 malaysia - kuala lumpur tel: 60-3-6201-9857 fax: 60-3-6201-9859 malaysia - penang tel: 60-4-227-8870 fax: 60-4-227-4068 philippines - manila tel: 63-2-634-9065 fax: 63-2-634-9069 singapore tel: 65-6334-8870 fax: 65-6334-8850 taiwan - hsin chu tel: 886-3-6578-300 fax: 886-3-6578-370 taiwan - kaohsiung tel: 886-7-536-4818 fax: 886-7-536-4803 taiwan - taipei tel: 886-2-2500-6610 fax: 886-2-2508-0102 thailand - bangkok tel: 66-2-694-1351 fax: 66-2-694-1350 europe austria - wels tel: 43-7242-2244-39 fax: 43-7242-2244-393 denmark - copenhagen tel: 45-4450-2828 fax: 45-4485-2829 france - paris tel: 33-1-69-53-63-20 fax: 33-1-69-30-90-79 germany - munich tel: 49-89-627-144-0 fax: 49-89-627-144-44 italy - milan tel: 39-0331-742611 fax: 39-0331-466781 netherlands - drunen tel: 31-416-690399 fax: 31-416-690340 spain - madrid tel: 34-91-708-08-90 fax: 34-91-708-08-91 uk - wokingham tel: 44-118-921-5869 fax: 44-118-921-5820 w orldwide s ales and s ervice 03/26/09 |
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